In the field of the semiconductor manufacturing, to electrically connect semiconductor devices, many types of metal interconnection structures and interconnection structure fabrication methods are developed, such as the copper interconnection structure and the electro-coppering plating method. However, as the development of the ultra-large scale integration (ULSI), characteristic dimension (CD) of the semiconductor devices continues shrinking. Thus, the methods for forming the metal interconnection structures are challenged.
FIG. 1 illustrates a sectional view of an exemplary conventional copper interconnection structure. As shown in FIG. 1, the process for forming the copper interconnection structure includes providing a substrate 100 having a first dielectric layer 101 and an exposed conductive layer 102 in the first dielectric layer 101; forming a second dielectric layer 103 on the first dielectric 101 and the conductive layer 102; forming openings in the second dielectric layer 103 to exposed the conductive layer 102, wherein the openings further include first sub-openings located on the top of the conductive layer 102, and second sub-openings located on top of the first sub-opening. That is, the first sub-openings and the second sub-openings form through openings. The size of the top end of the second sub-opening is larger than that of the first sub-opening. And, one or more the first sub-openings are formed at the bottom of the second sub-opening.
Further, a seed layer is formed on the surface of the second dielectric layer 103, and the sidewalls and the bottom surface of the openings. The seed layer is made of a conductive material. A copper material layer is formed on the surface of the seed layer using an electroplating process to fill the openings; and a copper interconnection structure 105 is formed by etching and removing portion of the copper material layer located on the second dielectric layer 103. In addition, the copper material layer located on the second dielectric layer 103 can also be removed by a chemical mechanical planarization process.
However, the current copper interconnection structure may have poor electrical performance. The disclosed methods are directed to solve one or more problems set forth above and other problems.